1. Field of the Invention
The present invention relates to a latency counter, and more particularly relates to a latency counter that counts a latency of an internal command within a synchronous memory. The present invention also relates to a semiconductor memory device including the latency counter, and a data processing system including the semiconductor memory device.
2. Description of Related Art
A synchronous memory represented by a synchronous DRAM (Dynamic Random Access Memory) is widely used for a main memory of a personal computer or the like. Because the synchronous memory can input and output data in synchronization with a clock signal supplied from a controller, a data transfer rate can be increased by using a faster clock.
However, even in the synchronous DRAM, operations performed by the DRAM core are only analog, and therefore it becomes necessary to amplify a very weak electric charge by performing a sense operation. Due to this, the duration between a time point at which a read command is issued and a time point at which first data is output cannot be shortened. Therefore, the first data is output, in synchronization with an external clock, after a predetermined delay time has elapsed from the time point at which the read command is issued.
This delay time is generally called “CAS latency” and it is set to an integral multiple of the clock cycle. For example, when the CAS latency is 5 (CL=5), the first data is output in synchronization with the external clock five cycles after the read command is retrieved in synchronization with the external clock. That is, the first data is output after five clock cycles have elapsed. A counter that counts such a latency is called “latency counter”.
As the latency counter, there has been known a circuit described in US2008/0043566-A1, which is proposed by the present inventor.
As mentioned in US2008/0043566-A1, the latency counter counts the latency in synchronization with an internal clock generated by a DLL (Delay Locked Loop) circuit. On the contrary, an external command supplied from outside is issued in synchronization with an external clock. Consequently, when a jitter component exists in either the external clock or the internal clock, there is a problem that a latch margin of the internal command is reduced.